Allwinner A20 - Page 373

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Offset Address: 0X012C
Register Name: CSI0_C1_BUF_STA_REG
Bit
Read/W
rite
Default/
Hex
Description
Indicates the CSI is capturing still image data (single frame). The
bit is set at the start of the first frame after enabling still frame
capture. It clears itself after the last pixel of the first frame is
captured.
For CCIR656 interface, if the output format is frame planar
YCbCr 420 mode, the frame end means the field2 end, the other
frame end means filed end.
4.1.5.26. CSI CHANNEL_1 INTERRUPT ENABLE REGISTER
Offset Address: 0X0130
Register Name: CSI0_C1_INT_EN_REG
Bit
Read/W
rite
Default/
Hex
Description
31:08
/
/
/
07
R/W
0
VS_INT_EN
vsync flag
The bit is set when vsync come. And at this time load the buffer
address for the coming frame. So after this irq come, change the
buffer address could only effect next frame
06
R/W
0
HB_OF_INT_EN
Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.
05
R/W
0
PRTC_ERR_INT_EN
04
R/W
0
FIFO2_OF_INT_EN
FIFO 2 overflow
The bit is set when the FIFO 2 become overflow.
03
R/W
0
FIFO1_OF_INT_EN
FIFO 1 overflow
The bit is set when the FIFO 1 become overflow.
02
R/W
0
FIFO0_OF_INT_EN
FIFO 0 overflow
The bit is set when the FIFO 0 become overflow.
01
R/W
0
FD_INT_EN
Frame done
Indicates the CSI has finished capturing an image frame. Applies
to video capture mode. The bit is set after each completed frame