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Allwinner A20 - Page 378

Allwinner A20
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A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 378 / 812
Offset Address: 0X0228
Register Name: CSI0_C2_BUF_CTL_REG
Bit
Read/W
rite
Default/H
ex
Description
selected by CSI module.
4.1.5.38. CSI CHANNEL_2 STATUS REGISTER
Offset Address: 0X022C
Register Name: CSI0_C2_BUF_STA_REG
Bit
Read/W
rite
Default/H
ex
Description
31:08
R
0
LUM_STATIS
luminance statistical value
When frame done interrupt flag come, value is ready and will
last until next frame done.
For raw data, value = (G>>1+R+G)>>8
For yuv422, value = Y>>8
07:02
/
/
/
01
R
0
VCAP_STA
Video capture in progress
Indicates the CSI is capturing video image data (multiple
frames). The bit is set at the start of the first frame after
enabling video capture. When software disables video capture,
it clears itself after the last pixel of the current frame is captured.
00
R
0
SCAP_STA
Still capture in progress
Indicates the CSI is capturing still image data (single frame).
The bit is set at the start of the first frame after enabling still
frame capture. It clears itself after the last pixel of the first frame
is captured.
For CCIR656 interface, if the output format is frame planar
YCbCr 420 mode, the frame end means the field2 end, the
other frame end means filed end.
4.1.5.39. CSI CHANNEL_2 INTERRUPT ENABLE REGISTER
Offset Address: 0X0230
Register Name: CSI0_C2_INT_EN_REG
Bit
Read/W
rite
Default/H
ex
Description

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