Allwinner A20 - Page 379

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Offset Address: 0X0230
Register Name: CSI0_C2_INT_EN_REG
Bit
Read/W
rite
Default/H
ex
Description
31:08
/
/
/
07
R/W
0
VS_INT_EN
vsync flag
The bit is set when vsync come. And at this time load the buffer
address for the coming frame. So after this irq come, change
the buffer address could only effect next frame
06
R/W
0
HB_OF_INT_EN
Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.
05
R/W
0
PRTC_ERR_INT_EN
04
R/W
0
FIFO2_OF_INT_EN
FIFO 2 overflow
The bit is set when the FIFO 2 become overflow.
03
R/W
0
FIFO1_OF_INT_EN
FIFO 1 overflow
The bit is set when the FIFO 1 become overflow.
02
R/W
0
FIFO0_OF_INT_EN
FIFO 0 overflow
The bit is set when the FIFO 0 become overflow.
01
R/W
0
FD_INT_EN
Frame done
Indicates the CSI has finished capturing an image frame.
Applies to video capture mode. The bit is set after each
completed frame capturing data is wrote to buffer as long as
video capture remains enabled.
00
R/W
0
CD_INT_EN
Capture done
Indicates the CSI has completed capturing the image data.
For still capture, the bit is set when one frame data has been
wrote to buffer.
For video capture, the bit is set when the last frame has been
wrote to buffer after video capture has been disabled.
For CCIR656 interface, if the output format is frame planar
YCbCr 420 mode, the frame end means the field2 end, the
other frame end means field end.