Allwinner A20 - Page 401

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 401 / 812
Offset Address: 0X0034
Register Name: CSI1_INT_STA_REG
Bit
Read/W
rite
Default/
Hex
Description
03
R/W
0
FIFO1_OF_PD
FIFO 1 overflow
02
R/W
0
FIFO0_OF_PD
FIFO 0 overflow
01
R/W
0
FD_PD
Frame done
00
R/W
0
CD_PD
Capture done
4.2.6.15. CSI CHANNEL_0 HORIZONTAL SIZE REGISTER
Offset Address: 0X0040
Register Name: CSI1_HSIZE_REG
Bit
Read/W
rite
Default/
Hex
Description
31:29
/
/
/
28:16
R/W
500
HOR_LEN
Horizontal pixel clock length. Valid pixel clocks of a line.
15:13
/
/
/
12:00
R/W
0
HOR_START
Horizontal pixel clock start.Pixel data is valid from this clock.
4.2.6.16. CSI CHANNEL_0 VERTICAL SIZE REGISTER
Offset Address: 0X0044
Register Name: CSI1_VSIZE_REG
Bit
Read/W
rite
Default/
Hex
Description