Allwinner A20 - Page 400

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 400 / 812
Offset Address: 0X0030
Register Name: CSI1_INT_EN_REG
Bit
Read/W
rite
Default/
Hex
Description
02
R/W
0
FIFO0_OF_INT_EN
FIFO 0 overflow
The bit is set when the FIFO 0 become overflow.
01
R/W
0
FD_INT_EN
Frame done
Indicates the CSI has finished capturing an image frame. Applies
to video capture mode. The bit is set after each completed frame
capturing data is wrote to buffer as long as video capture
remains enabled.
00
R/W
0
CD_INT_EN
Capture done
Indicates the CSI has completed capturing the image data.
For still capture, the bit is set when one frame data has been
wrote to buffer.
For video capture, the bit is set when the last frame has been
wrote to buffer after video capture has been disabled.
For CCIR656 interface, if the output format is frame planar
YCbCr 420 mode, the frame end means the field2 end, the other
frame end means field end.
4.2.6.14. CSI CHANNEL_0 INTERRUPT STATUS REGISTER
Offset Address: 0X0034
Register Name: CSI1_INT_STA_REG
Bit
Read/W
rite
Default/
Hex
Description
31:08
/
/
/
07
R/W
0
VS_PD
vsync flag
06
R/W
0
HB_OF_PD
Hblank FIFO overflow
05
R/W
0
PRTC_ERR_PD
04
R/W
0
FIFO2_OF_PD
FIFO 2 overflow