Allwinner A20 - Page 399

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 399 / 812
Offset Address: 0X002C
Register Name: CSI1_BUF_STA_REG
Bit
Read/W
rite
Default/
Hex
Description
video capture. When software disables video capture, it clears
itself after the last pixel of the current frame is captured.
00
R
0
SCAP_STA
Still capture in progress
Indicates the CSI is capturing still image data (single frame). The
bit is set at the start of the first frame after enabling still frame
capture. It clears itself after the last pixel of the first frame is
captured.
For CCIR656 interface, if the output format is frame planar
YCbCr 420 mode, the frame end means the field2 end, the other
frame end means filed end.
4.2.6.13. CSI CHANNEL_0 INTERRUPT ENABLE REGISTER
Offset Address: 0X0030
Register Name: CSI1_INT_EN_REG
Bit
Read/W
rite
Default/
Hex
Description
31:08
/
/
/
07
R/W
0
VS_INT_EN
vsync flag
The bit is set when vsync come. And at this time load the buffer
address for the coming frame. So after this irq come, change the
buffer address could only effect next frame
06
R/W
0
HB_OF_INT_EN
Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.
05
R/W
0
PRTC_ERR_INT_EN
04
R/W
0
FIFO2_OF_INT_EN
FIFO 2 overflow
The bit is set when the FIFO 2 become overflow.
03
R/W
0
FIFO1_OF_INT_EN
FIFO 1 overflow
The bit is set when the FIFO 1 become overflow.