Allwinner A20 - Page 422

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 422 / 812
5.1.4.20. TCON0 LVDS PANEL INTERFACE REGISTER
Offset: 0x084
Register Name: TCON0_LVDS_IF_REG
Bit
Read/
Write
Default/
Hex
Description
31
R/W
0
TCON0_LVDS_En
0: disable
1: enable
30:29
/
/
/
28
R/W
0
TCON0_LVDS_Dir
1: normal
2: reverse
NOTE: LVDS direction
27
R/W
0
TCON0_LVDS_Mode
0: NS mode
1: JEIDA mode
26
R/W
0
TCON0_LVDS_BitWidth
0: 24bit
1: 18bit
25:24
R/W
0
/
23
R/W
0
TCON0_LVDS_Correct_Mode
0: mode0
1: mode1
22:0
/
/
/
5.1.4.21. TCON0 IO POLARITY REGISTER
Offset: 0x088
Register Name: TCON0_IO_POL_REG
Bit
Read/
Write
Default/
Hex
Description
31:30
/
/
/
29:28
R/W
0
DCLK_Sel
00: used DCLK0(normal phase offset)
01: used DCLK1(1/3 phase offset)
10: used DCLK2(2/3 phase offset)
11: reserved