Allwinner A20 - Page 424

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 424 / 812
Offset: 0x08C
Register Name: TCON0_IO_TRI_REG
Bit
Read/
Write
Default/H
ex
Description
24
R/W
1
IO0_Output_Tri_En
1: disable
0: enable
23:0
R/W
0xFFFFFF
Data_Output_Tri_En
TCON0 output port D[23:0] output enable, with independent bit
control:
1s: disable
0s: enable
5.1.4.23. TCON1 CONTROL REGISTER
Offset: 0x090
Register Name: TCON1_CTL_REG
Bit
Read/
Write
Default/
Hex
Description
31
R/W
0
TCON1_En
0: disable
1: enable
30:21
/
/
/
20
R/W
0
Interlace_En
0:disable
1:enable
19:9
/
/
/
8:4
R/W
0
Start_Delay
This is for DE1 and DE2
3:2
/
/
/
1:0
R/W
0
TCON1_Src_Sel
00: DE CH1(FIFO2 enable)
01: DE CH2(FIFO2 enable)
1x: BLUE data(FIFO2 disable, RGB=0000FF)