Allwinner A20 - Page 462

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 462 / 812
5.2.4.26. PLL/DRV SETTING 2: PLL CTRL0
Offset: 0x208
Register name: PLL_Ctrl
Bits
Read
/Write
Default
/Hex
Description
31
R/W
0
PLL_EN
30
R/W
0
BWS
29
R/W
0
HV_IS_33
28
R/W
0
LDO1_EN
27
R/W
0
LDO2_EN
26
R/W
0
S6P25_7P5
25
R/W
0
SDIV2
24
R/W
0
SINT_FRAC
23
R/W
0
VCO_GAIN_EN
22:20
R/W
0
VCO_GAIN
19:17
R/W
0
S
16:12
R/W
0
CP_S
11:8
R/W
0
CS
7:4
R/W
0
PREDIV
3:0
R/W
0
VCO_S
5.2.4.27. PLL/DRV SETTING 3: PLL DBG0
Offset: 0x20c
Register name: PLL_Dbg0
Bits
Read
/Write
Default
/Hex
Description
31
R/W
0
PLL_DBG_EN
30:28
R/W
0
PSET
27:26
R/W
0
CLKSTEP
25:24
R/W
0
PDCLKSEL
23
R/W
0
S5_7
22
R/W
0
/
21
R/W
0
CKIN_SEL