Allwinner A20 - Page 476

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 476 / 812
Offset: 0x524
Register name: DDC_ExREG
Bits
Read
/Write
Default
/Hex
Description
0: disable
1: enable
0
R/W
0
DDC_SDA_LineState_Control_Bit
When DDC_ SDA line state control enable is set to ‘1’, the value
of this bit decide the output level of DDC_ SDA
0: output low level
1: output high level
5.2.4.43. DDC CLOCK REGISTER
Offset: 0x528
Register name: DDC_Clock
Bits
Read
/Write
Default
/Hex
Description
31:7
/
/
reserved
6:3
R/W
0
M
Note: M is recommend set to value greater than 0.
2:0
R/W
0
N
The DDC bus is sampled by the DCC at the frequency defined by
F0:
Fs =F0 = Fin/2^N
The DDC output frequency is F1/10/:
F1 = F0/(M+1)
Foscl = F1/10 = Fin/(2^N * (M+1) *10
The source clock frequency is the f
TMDS
/2.