Allwinner A20 - Page 493

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 493 / 812
Offset: 0x4C
Register Name: DEFE_INPUT_FMT_REG
Bit
Read/
Write
Default/H
ex
Description
Pixel sequence
In interleaved YUV422 data mode:
00: Y1V0Y0U0
01: V0Y1U0Y0
10: Y1U0Y0V0
11: U0Y1V0Y0
In interleaved YUV444 data mode:
00: VUYA
01: AYUV
Other: reserved
In UV combined data mode: (UV component)
00: V1U1V0U0
01: U1V1U0V0
Other: reserved
In interleaved ARGB8888 data mode:
00: BGRA
01: ARGB
Other: reserved
5.3.4.17. DEFE_WB_ADDR0_REG
Offset: 0x50
Register Name: DEFE_WB_ADDR0_REG
Bit
Read/
Write
Default/H
ex
Description
31:0
R/W
0x0
WB_ADDR
Write-back address setting for scaled data.