Allwinner A20 - Page 537

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 537 / 812
Offset: 0x860
Register Name: DEBE_LAYFB_H4ADD_REG
Bit
Read/W
rite
Default/
Hex
Description
27:24
R/W
UDF
LAY3FB_H4ADD
Layer3
Layer Frame Buffer Address in bit
23:20
/
/
/
19:16
R/W
UDF
LAY2FB_H4ADD
Layer2
Layer Frame Buffer Address in bit
15:12
/
/
/
11:8
R/W
UDF
LAY1FB_H4ADD
Layer1
Layer Frame Buffer Address in bit
7:4
/
/
/
3:0
R/W
UDF
LAY0FB_H4ADD
Layer0
Layer Frame Buffer Address in bit
Note: If the layer is selected by video channel or YUV channel, the setting of this register will
be ignored.
5.4.4.9. DE-REGISTER BUFFER CONTROL REGISTER
Offset: 0x870
Register Name: DEBE_REGBUFFCTL_REG
Bit
Read/W
rite
Default/
Hex
Description
31:2
/
/
/
1
R/W
0X00
REGAUTOLOAD_DIS
Module registers loading auto mode disable control
0: registers auto loading mode
1: disable registers auto loading mode, the registers will be
loaded by write 1 to bit0 of this register
0
R/W
0X00
REGLOADCTL
Register load control
When the Module registers loading auto mode disable control bit
is set, the registers will be loaded by write 1 to the bit, and the bit