Allwinner A20 - Page 56

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 56 / 812
Offset: 0x6C
Register Name: APB1_GATING_REG
Bit
Read/
Write
Default/He
x
Description
20
R/W
0x0
UART4_APB_GATING.
Gating APB Clock for UART4(0: mask, 1: pass).
19
R/W
0x0
UART3_APB_GATING.
Gating APB Clock for UART3(0: mask, 1: pass).
18
R/W
0x0
UART2_APB_GATING.
Gating APB Clock for UART2(0: mask, 1: pass).
17
R/W
0x0
UART1_APB_GATING.
Gating APB Clock for UART1(0: mask, 1: pass).
16
R/W
0x0
UART0_APB_GATING.
Gating APB Clock for UART0(0: mask, 1: pass).
15
R/W
0x0
TWI4_APB_GATING.
Gating APB Clock for TWI4(0: mask, 1: pass).
14:8
/
/
/
7
R/W
0x0
PS21_APB_GATING.
Gating APB Clock for PS2-1(0: mask, 1: pass).
6
R/W
0x0
PS20_APB_GATING.
Gating APB Clock for PS2-0(0: mask, 1: pass).
5
R/W
0x0
SCR_APB_GATING.
Gating APB Clock for SCR(0: mask, 1: pass).
4
R/W
0x0
CAN_APB_GATING.
Gating APB Clock for CAN(0: mask, 1: pass).
3
R/W
0x0
TWI3_APB_GATING.
Gating APB Clock for TWI3(0: mask, 1: pass).
2
R/W
0x0
TWI2_APB_GATING.
Gating APB Clock for TWI2(0: mask, 1: pass).
1
R/W
0x0
TWI1_APB_GATING.
Gating APB Clock for TWI1(0: mask, 1: pass).
0
R/W
0x0
TWI0_APB_GATING.
Gating APB Clock for TWI0(0: mask, 1: pass).