Allwinner A20 - Page 55

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 55 / 812
Offset: 0x68
Register Name: APB0_GATING_REG
Bit
Read/
Write
Default/He
x
Description
9
/
/
/
8
R/W
0x0
IIS2_APB_GATING.
Gating APB Clock for IIS2(0: mask, 1: pass).
7
R/W
0x0
IR1_APB_GATING.
Gating APB Clock for IR1(0: mask, 1: pass).
6
R/W
0x0
IR0_APB_GATING.
Gating APB Clock for IR0(0: mask, 1: pass).
5
R/W
0x0
PIO_APB_GATING.
Gating APB Clock for PIO(0: mask, 1: pass).
4
R/W
0x0
IIS1_APB_GATING.
Gating APB Clock for IIS1(0: mask, 1: pass).
3
R/W
0x0
IIS0_APB_GATING.
Gating APB Clock for IIS0(0: mask, 1: pass).
2
R/W
0x0
AC97_APB_GATING.
Gating APB Clock for AC97(0: mask, 1: pass).
1
R/W
0x0
SPDIF_APB_GATING.
Gating APB Clock for SPDIF(0: mask, 1: pass).
0
R/W
0x0
CODEC_APB_GATING.
Gating APB Clock for Audio CODEC(0: mask, 1: pass).
1.5.4.21. APB1 MODULE CLOCK GATING(DEFAULT: 0X00000000)
Offset: 0x6C
Register Name: APB1_GATING_REG
Bit
Read/
Write
Default/He
x
Description
31:24
/
/
/.
23
R/W
0x0
UART7_APB_GATING.
Gating APB Clock for UART7(0: mask, 1: pass).
22
R/W
0x0
UART6_APB_GATING.
Gating APB Clock for UART6(0: mask, 1: pass).
21
R/W
0x0
UART5_APB_GATING.
Gating APB Clock for UART5(0: mask, 1: pass).