Allwinner A20 - Page 54

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 54 / 812
Offset: 0x64
Register Name: AHB_GATING_REG1
Bit
Read/
Write
Default/Hex
Description
31:21
/
/
/.
20
R/W
0x0
Gating AHB Clock for Mali-400(0: mask, 1: pass).
19
/
/
/
18
R/W
0x0
Gating AHB Clock for MP(0: mask, 1: pass).
17
R/W
0x0
GMAC_AHB_GATING
Gating AHB Clock for GMAC(0:mask,1:pass)
16
/
/
/
15
R/W
0x0
Gating AHB Clock for DE-FE1(0: mask, 1: pass).
14
R/W
0x0
Gating AHB Clock for DE-FE0(0: mask, 1: pass).
13
R/W
0x0
Gating AHB Clock for DE-BE1(0: mask, 1: pass).
12
R/W
0x0
Gating AHB Clock for DE-BE0(0: mask, 1: pass).
11
R/W
0x0
Gating AHB Clock for HDMI(0: mask, 1: pass).
10
R/W
0x0
Gating AHB Clock for HDMI1(0: mask, 1: pass).
9
R/W
0x0
Gating AHB Clock for CSI1(0: mask, 1: pass).
8
R/W
0x0
Gating AHB Clock for CSI0(0: mask, 1: pass).
7:6
/
/
5
R/W
0x0
Gating AHB Clock for LCD1(0: mask, 1: pass).
4
R/W
0x0
Gating AHB Clock for LCD0(0: mask, 1: pass).
3
R/W
0x0
Gating AHB Clock for TVE 1(0: mask, 1: pass).
2
R/W
0x0
Gating AHB Clock for TVE 0(0: mask, 1: pass).
1
R/W
0x0
Gating AHB Clock for TVD(0: mask, 1: pass).
0
R/W
0x0
Gating AHB Clock for VE(0: mask, 1: pass).
1.5.4.20. APB0 MODULE CLOCK GATING(DEFAULT: 0X00000000)
Offset: 0x68
Register Name: APB0_GATING_REG
Bit
Read/
Write
Default/He
x
Description
31:11
/
/
/.
10
R/W
0x0
KEYPAD_APB_GATING.
Gating APB Clock for Keypad(0: mask, 1: pass).