Allwinner A20 - Page 53

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 53 / 812
Offset: 0x60
Register Name: AHB_GATING_REG0
Bit
Read/
Write
Default/Hex
Description
23
R/W
0x0
Gating AHB Clock for SPI3(0: mask, 1: pass).
22
R/W
0x0
Gating AHB Clock for SPI2(0: mask, 1: pass).
21
R/W
0x0
Gating AHB Clock for SPI1(0: mask, 1: pass).
20
R/W
0x0
Gating AHB Clock for SPI0(0: mask, 1: pass).
19
/
/
/
18
R/W
0x0
Gating AHB Clock for TS(0: mask, 1: pass).
17
R/W
0x0
Gating AHB Clock for EMAC(0: mask, 1: pass).
16
R/W
0x0
Gating AHB Clock for ACE(0: mask, 1: pass).
15
/
/
/
14
R/W
0x0
Gating AHB Clock for SDRAM(0: mask, 1: pass).
13
R/W
0x0
Gating AHB Clock for NAND(0: mask, 1: pass).
12
R/W
0x0
Gating AHB Clock for MS(0: mask, 1: pass).
11
R/W
0x0
Gating AHB Clock for SD/MMC3(0: mask, 1: pass).
10
R/W
0x0
Gating AHB Clock for SD/MMC2(0: mask, 1: pass).
9
R/W
0x0
Gating AHB Clock for SD/MMC1(0: mask, 1: pass).
8
R/W
0x0
Gating AHB Clock for SD/MMC0(0: mask, 1: pass).
7
R/W
0x0
Gating AHB Clock for BIST(0: mask, 1: pass).
6
R/W
0x0
Gating AHB Clock for DMA(0: mask, 1: pass).
5
R/W
0x0
Gating AHB Clock for SS(0: mask, 1: pass).
4
R/W
0x0
Gating AHB Clock for USB OHCI1(0: mask, 1: pass).
3
R/W
0x0
Gating AHB Clock for USB EHCI1 (0: mask, 1: pass).
2
R/W
0x0
Gating AHB Clock for USB OHCI0(0: mask, 1: pass).
1
R/W
0x0
Gating AHB Clock for USB EHCI0 (0: mask, 1: pass).
0
R/W
0x0
Gating AHB Clock for USB0(0: mask, 1: pass).
1.5.4.19. AHB MODULE CLOCK GATING REGISTER 1(DEFAULT: 0X00000000)
Offset: 0x64
Register Name: AHB_GATING_REG1
Bit
Read/
Write
Default/Hex
Description