Allwinner A20 - Page 573

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 573 / 812
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0 R0 G0 B0

1 R1 G1 B1
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254 R254 G254 B254

255 R255 G255 B255

n Rn Gn Bn
On chip SRAM array
5 38 133 28
Inputting external
frame buffer data
Output color

5 R38 G133 B28
On chip SRAM for gamma correction
5.4.4.56. DISPLAY ENGINE MEMORY MAPPING
Registers
0x0800
0x0DFF
Reserved
0x3FFF
Reserved
0x0E00
0x4000
Gamma Table
0x43FF
0x4400
0x47FF
HWC Palette Table
0x4C00
0x4FFF
PIPE0 Palette Table
0x5000
0x53FF
0x5400
0xFFFF
0x57FF
0x5800
HWC Memory Block
0x4800
0x4BFF
PIPE1 Palette Table
Reserved
Base Address:
BE0: 0x01e60000
BE1: 0x01e40000
Offset:
Reserved
0x0000
0x07FF