Allwinner A20 - Page 58

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 58 / 812
Offset: 0x84
Register Name: MS_SCLK_CFG_REG
Bit
Read/
Write
Default/Hex
Description
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL6
10: PLL5
11: /.
23:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is
1/2/4/8.
15:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1
to 16.
1.5.4.24. SD/MMC 0 CLOCK(DEFAULT: 0X00000000)
Offset: 0x88
Register Name: SD0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select