Allwinner A20 - Page 59

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 59 / 812
Offset: 0x88
Register Name: SD0_CLK_REG
Bit
Read/
Write
Default/Hex
Description
00: OSC24M
01: PLL6
10: PLL5
11: /.
23
/
/
/
22:20
R/W
0x0
CLK_PHASE_CTR.
Sample Clock Phase Control.
The sample clock phase delay is based on the number of
source clock that is from 0 to 7.
19:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is
1/2/4/8.
15:11
/
/
/
10:8
R/W
0x0
OUTPUT_CLK_PHASE_CTR.
Output Clock Phase Control.
The output clock phase delay is based on the number of
source clock that is from 0 to 7.
7:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1
to 16.
1.5.4.25. SD/MMC 1 CLOCK(DEFAULT: 0X00000000)
Offset: 0x8C
Register Name: SD1_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON