Allwinner A20 - Page 580

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 580 / 812
Note:
For 7-bit addressing:
SLA6 – SLA0 is the 7-bit address of the TWI when in slave mode. When the TWI receives this
address after a START condition, it will generate an interrupt and enter slave mode. (SLA6
corresponds to the first bit received from the 2-Wire bus.) If GCE is set to ‘1’, the TWI will also
recognize the general call address (00h).
For 10-bit addressing:
When the address received starts with 11110b, the TWI recognizes this as the first part of a 10-bit
address and if the next two bits match ADDR[2:1] (i.e. SLAX9 and SLAX8 of the device’s extended
address), it sends an ACK. (The device does not generate an interrupt at this point.) If the next byte
of the address matches the XADDR register (SLAX7 – SLAX0), the TWI generates an interrupt and
goes into slave mode.
6.2.4.2. TWI EXTEND ADDRESS REGISTER
Offset: 0x04
Register Name: TWI_XADDR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
7:0
R/W
0
SLAX
Extend Slave Address
SLAX[7:0]
6.2.4.3. TWI DATA REGISTER
Offset: 0x08
Register Name: TWI_DATA
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
7:0
R/W
0
TWI_DATA
Data byte for transmitting or received