INT_FLAG
Interrupt Flag
INT_FLAG is automatically set to ‘1’ when any of 28 (out of
the possible 29) states is entered (see ‘STAT Register’
below). The only state that does not set INT_FLAG is state
F8h. If the INT_EN bit is set, the interrupt line goes high
when IFLG is set to ‘1’. If the TWI is operating in slave
mode, data transfer is suspended when INT_FLAG is set
and the low period of the 2-wire bus clock line (SCL) is
stretched until ‘0’ is written to INT_FLAG. The 2-wire clock
line is then released and the interrupt line goes low.
A_ACK
Assert Acknowledge
When A_ACK is set to ‘1’, an Acknowledge (low level on
SDA) will be sent during the acknowledge clock pulse on
the 2-Wire bus if:
a. Either the whole of a matching 7-bit slave address or the
first or the second byte of a matching 10-bit slave address
has been received.
b. The general call address has been received and the GCE
bit in the ADDR register is set to ‘1’.
c. A data byte has been received in master or slave mode.
When A_ACK is ‘0’, a Not Acknowledge (high level on SDA)
will be sent when a data byte is received in master or slave
mode.
If A_ACK is cleared to ‘0’ in slave transmitter mode, the byte
in the DATA register is assumed to be the ‘last byte’. After
this byte has been transmitted, the TWI will enter state C8h
then return to the idle state (status code F8h) when
INT_FLAG is cleared.
The TWI will not respond as a slave unless A_ACK is set.
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