Allwinner A20 - Page 584

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 584 / 812
Offset: 0x10
Register Name: TWI_STAT
Default Value: 0x0000_00F8
Bit
Read/Write
Default
Description
0xC8: Last byte transmitted in slave mode, ACK received
0xD0: Second Address byte + Write bit transmitted, ACK received
0xD8: Second Address byte + Write bit transmitted, ACK not
received
0xF8: No relevant status information, INT_FLAG=0
Others: Reserved
6.2.4.6. TWI CLOCK REGISTER
Offset: 0x14
Register Name: TWI_CCR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:7
/
/
/
6:3
R/W
0
CLK_M
2:0
R/W
0
CLK_N
The 2-Wire bus is sampled by the TWI at the frequency
defined by F0:
Fsamp = F 0 = Fin / 2^CLK_N
The TWI OSCL output frequency, in master mode, is F1 / 10:
F1 = F0 / (CLK_M + 1)
Foscl = F1 / 10 = Fin / (2^CLK_N * (CLK_M + 1)*10)
For Example:
Fin = 48Mhz (APB clock input)
For 400kHz full speed 2Wire, CLK_N = 2, CLK_M=2
F0 = 48M/2^2=12Mhz, F1= F0/(10*(2+1)) = 0.4Mhz
For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11
F0=48M/2^2=12Mhz, F1=F0/(10*(11+1)) = 0.1Mhz
TWI SOFT RESET REGISTER
Offset: 0x18
Register Name: TWI_SRST
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description