Allwinner A20 - Page 586

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 586 / 812
Offset: 0x20
Register Name: TWI_LCR
Default Value: 0x0000_003a
Bit
Read/Write
Default
Description
0 – low
1 - high
3
R/W
1
SCL_CTL
TWI_SCL line state control bit
When line control mode is enabled (bit[2] set), value of this bit
decide the output level of TWI_SCL
0 – output low level
1 – output high level
2
R/W
0
SCL_CTL_EN
TWI_SCL line state control enable
When this bit is set, the state of TWI_SCL is control by the
value of bit[3].
0-disable TWI_SCL line control mode
1-enable TWI_SCL line control mode
1
R/W
1
SDA_CTL
TWI_SDA line state control bit
When line control mode is enabled (bit[0] set), value of this bit
decide the output level of TWI_SDA
0 – output low level
1 – output high level
0
R/W
0
SDA_CTL_EN
TWI_SDA line state control enable
When this bit is set, the state of TWI_SDA is control by the
value of bit[1].
0-disable TWI_SDA line control mode
1-enable TWI_SDA line control mode
6.2.4.9. TWI DVFS CONTROL REGISTER
Offset: 0x24
Register Name: TWI_DVFSCR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:2
/
/
/