Allwinner A20 - Page 596

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 596 / 812
Offset: 0x08
Register Name: SPI_CTL
Default Value: 0x0012_001C
Bit
Read/Write
Default
Description
0: Slave Mode
1: Master Mode
0
R/W
0
EN
SPI Module Enable Control
0: Disable
1: Enable
6.3.4.4. SPI INTERRUPT CONTROL REGISTER
Offset: 0x0C
Register Name: SPI_INTCTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:18
/
/
/
17
R/W
0
SS_INT_EN
SSI Interrupt Enable
Chip Select Signal (SSx) from valid state to invalid state
0: Disable
1: Enable
16
R/W
0
TX_INT_EN
Transfer Completed Interrupt Enable
0: Disable
1: Enable
15
/
/
/
14
R/W
0
TF_UR_INT_EN
TXFIFO under run Interrupt Enable
0: Disable
1: Enable
13
R/W
0
TF_OF_INT_EN
TX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
12
R/W
0
TF_E34_INT_EN