Allwinner A20 - Page 598

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 598 / 812
Offset: 0x0C
Register Name: SPI_INTCTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
0: Disable
1: Enable
2
R/W
0
RF_FU_INT_EN
RX FIFO Full Interrupt Enable
0: Disable
1: Enable
1
R/W
0
RF_HALF_FU_INT_EN
RX FIFO Half Full Interrupt Enable
0: Disable
1: Enable
0
R/W
0
RF_RDY_INT_EN
RX FIFO Ready Interrupt Enable
0: Disable
1: Enable
6.3.4.5. SPI INTERRUPT STATUS REGISTER
Offset: 0x10
Register Name: SPI_INT_STA
Default Value: 0x0000_1B00
Bit
Read/Write
Default
Description
31
R
0
INT_CBF
Interrupt Clear Busy Flag
0: clear interrupt flag done
1; clear interrupt flag busy
30:18
/
/
/
17
R/W
0
SSI
SS Invalid Interrupt
When SSI is 1, it indicates that SS has changed from valid
state to invalid state. Writing 1 to this bit clears it.
16
R/W
0
TC
Transfer Completed
In master mode, it indicates that all bursts specified by BC has
been exchanged. In other condition, When set, this bit