A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 610 / 812
Register Name: UART_RBR
Default Value: 0x0000_0000
or the serial infrared input (sir_in) in infrared mode. The data in
this register is valid only if the Data Ready (DR) bit in the Line
Status Register (LCR) is set.
If in FIFO mode and FIFOs are enabled (FCR[0] set to one), this
register accesses the head of the receive FIFO. If the receive
FIFO is full and this register is not read before the next data
character arrives, then the data already in the FIFO is
preserved, but any incoming data are lost and an overrun error
occurs.
6.4.4.2. UART TRANSMIT HOLDING REGISTER
Register Name: UART_THR
Default Value: 0x0000_0000
THR
Transmit Holding Register
Data to be transmitted on the serial output port (sout) in UART
mode or the serial infrared output (sir_out_n) in infrared mode.
Data should only be written to the THR when the THR Empty
(THRE) bit (LSR[5]) is set.
If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and
THRE is set, 16 number of characters of data may be written
to the THR before the FIFO is full. Any attempt to write data
when the FIFO is full results in the write data being lost.
6.4.4.3. UART DIVISOR LATCH LOW REGISTER
Register Name: UART_DLL
Default Value: 0x0000_0000
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