Allwinner A20 - Page 618

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 618 / 812
6.4.4.9. UART MODEM CONTROL REGISTER
Offset: 0x10
Register Name: UART_MCR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:7
/
/
/
6
R/W
0
SIRE
SIR Mode Enable
0: IrDA SIR Mode disabled
1: IrDA SIR Mode enabled
5
R/W
0
AFCE
Auto Flow Control Enable
When FIFOs are enabled and the Auto Flow Control Enable
(AFCE) bit is set, Auto Flow Control features are enabled.
0: Auto Flow Control Mode disabled
1: Auto Flow Control Mode enabled
4
R/W
0
/
3:2
/
/
/
1
R/W
0
RTS
Request to Send
This is used to directly control the Request to Send (rts_n)
output. The Request To Send (rts_n) output is used to inform
the modem or data set that the UART is ready to exchange
data. When Auto RTS Flow Control is not enabled (MCR[5] set
to zero), the rts_n signal is set low by programming MCR[1]
(RTS) to a high.In Auto Flow Control, AFCE_MODE ==
Enabled and active (MCR[5] set to one) and FIFOs enable
(FCR[0] set to one), the rts_n output is controlled in the same
way, but is also gated with the receiver FIFO threshold trigger
(rts_n is
inactive high when above the threshold). The rts_n signal is
de-asserted when MCR[1] is set low.
0: rts_n de-asserted (logic 1)
1: rts_n asserted (logic 0)
Note that in Loopback mode (MCR[4] set to one), the rts_n
output is held inactive high while the value of this location is
internally looped back to an input.
0
R/W
0
DTR