Allwinner A20 - Page 638

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 638 / 812
Offset: 0x0010
Register Name: PS2_FCTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
17
R/W
0
TXFIFO_RST
TXFIFO Reset
After this bit is set, data in TXFIFO is flushed, and the pointer
of TXFIFO is reset.
Note: This bit is cleared automatically after TXFIFO is reset,
and writing ‘0’ has no effect.
16
R/W
0
RXFIFO_RST
RXFIFO Reset
After this bit is set, data in RXFIFO is flushed, and the pointer
of RXFIFO is reset.
Note: This bit is cleared automatically after RXFIFO is reset,
and writing ‘0’ has no effect.
15:11
/
/
/
10
R/W
0
TXUF_IEN
TXFIFO Underflow Interrupt Enable
9
R/W
0
TXOF_IEN
TXFIFO Overflow Interrupt Enable
8
R/W
0
TXRDY_IEN
TXFIFO Ready Interrupt Enable
7:3
/
/
/
2
R/W
0
RXUF_IEN
RXFIFO Underflow Interrupt Enable
1
R/W
0
RXOF_IEN
RXFIFO Overflow Interrupt Enable
0
R/W
0
RXRDY_IEN
RXFIFO Ready Interrupt Enable
6.5.5.6. PS2 FIFO STATUS REGISTER
Offset: 0x0014
Register Name: PS2_FSTS
Default Value: 0x0000_0100
Bit
Read/Write
Default
Description