Allwinner A20 - Page 644

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 644 / 812
Offset: 0x00
Register Name: IR_CTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
2
R/W
0
TXEN
Transmitter Block Enable
0: Disable
1: Enable
1
R/W
0
RXEN
Receiver Block Enable
0: Disable
1: Enable
0
R/W
0
GEN
Global Enable
A disable on this bit overrides any other block or channel
enables and flushes all FIFOs.
0: Disable
1: Enable
6.6.3.2. IR TRANSMITTER CONFIGURE REGISTER
Offset: 0x04
Register Name: IR_TXCTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:6
/
/
/
5
R/W
0
PCF
Packet Complete by FIFO
This bit determines how a packet is completed if a TX FIFO
underrun event occurs. Do not write software intentionally to
cause underrun events. However, if due to erroneous
conditions, the value of this bit selects between two recovery
modes. Set the PCF based on system and upper layer IrDA
protocol requirements.
0: Send CRC and STO fields
Send CRC16 and STO for MIR or CRC32 and STO for FIR
1: Send packet abort symbol
Send 7’b111,1111 for MIR or 8’b0000,0000 for FIR
4
/
/
/
3
R/W
0
SIP