Allwinner A20 - Page 647

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 647 / 812
Offset: 0x10
Register Name: IR_RXCTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
1: Invert receiver signal
1:0
/
/
/
6.6.3.6. IR RECEIVER ADDRESS REGISTER
Offset: 0x14
Register Name: IR_RXADR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:9
/
/
/
8
R/W
0
RAM
Receiver Address Match
0: Does not need match address (RA). When an new packet is
received, the address, control and data fields are filled into RX
FIFO.
1: Should match packet address to RA bits when an new
packet is received. If address matched, the control and data
fields are filled into RX FIFO excluding the address field.
The value of this bit can be changed when the RXEN bit is
cleared.
7:0
R/W
0
RA
Receiver Address
The value of this bit can be changed when the RXEN bit is
cleared.
6.6.3.7. IR RECEIVER COUNTER REGISTER
Offset: 0x18
Register Name: IR_RXCNT
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:12
/
/
/
11:0
R
0
RPL
Receiver Packet Length