Allwinner A20 - Page 649

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 649 / 812
Bit
Read/Write
Default
Description
31:12
/
/
/
11:8
R/W
0
TEL
TX FIFO Empty Level for interrupt and DMA request
TRIGGER_LEVEL = TEL + 1
7:6
/
/
/
5
R/W
0
DRQ_EN
TX FIFO Empty DMA Enable
0: Disable
1: Enable
When set to ‘1’, the Transmitter FIFO DRQ is asserted if
reaching TEL. The DRQ is de-asserted when condition fails or
specified number data has been sent from host CPU.
4
R/W
0
TEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, the Transmitter FIFO interrupt is asserted if
reaching TEL. The interrupt is de-asserted when condition fails
or specified number data has been sent from host CPU.
3
R/W
0
TCI_EN
Transmit (including the CRC and STO fields) Complete
Interrupt Enable
0: Disable
1: Enable
2
R/W
0
SIPEI_EN
Transmitter SIP End Interrupt Enable
0: Disable
1: Enable
1
R/W
0
TPEI_EN
Transmitter Packet (the address, control and data fields) End
Interrupt Enable
0: Disable
1: Enable
0
R/W
0
TUI_EN
Transmitter FIFO Under run Interrupt Enable
0: Disable
1: Enable