Allwinner A20 - Page 650

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 650 / 812
6.6.3.11. IR TRANSMITTER STATUS REGISTER
Offset: 0x28
Register Name: IR_TXSTA
Default Value: 0x0000_1000
Bit
Read/Write
Default
Description
31:13
/
/
/
12:8
R
0x10
TA
TX FIFO Available Room Counter
0: TX FIFO full
1: TX FIFO 1 byte room for new data
2: TX FIFO 2 byte room for new data
…
15: TX FIFO 15 byte room for new data
16: TX FIFO 16 byte room for new data (full empty)
Others: Reserved
7:5
/
/
/
4
R/W
1
TE
TX FIFO Empty
0: TX FIFO not empty
1: TX FIFO empty by its level
This bit is cleared by writing a ‘1’.
3
R/W
0
TC
Transmit (including the CRC and STO fields) Complete
0: Transmission not completed
1: Transmission completed
This bit is cleared by writing a ‘1’.
2
R/W
0
SIPE
Transmitter SIP End
0: Transmission of SIP not completed
1: Transmission of SIP completed
This bit is cleared by writing a ‘1’.
1
R/W
0
TPE
Transmitter Packet End
0: Transmissions of address, control and data fields not
completed
1: Transmissions of address, control and data fields completed