Allwinner A20 - Page 651

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 651 / 812
Offset: 0x28
Register Name: IR_TXSTA
Default Value: 0x0000_1000
Bit
Read/Write
Default
Description
This bit is cleared by writing a ‘1’.
0
R/W
0
TU
Transmitter FIFO Under Run
0: No transmitter FIFO under run
1: Transmitter FIFO under run
This bit is cleared by writing a ‘1’.
6.6.3.12. IR RECEIVER INTERRUPT CONTROL REGISTER
Offset: 0x2C
Register Name: IR_RXINT
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:12
/
/
/
11:8
R/W
0
RAL
RX FIFO Available Received Byte Level for interrupt and DMA
request
TRIGGER_LEVEL = RAL + 1
7:6
/
/
/
5
R/W
0
DRQ_EN
RX FIFO DMA Enable
0: Disable
1: Enable
When set to ‘1’, the Receiver FIFO DRQ is asserted if
reaching RAL. The DRQ is de-asserted when condition fails.
4
R/W
0
RAI_EN
RX FIFO Available Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, the Receiver FIFO IRQ is asserted if reaching
RAL. The IRQ is de-asserted when condition fails.
3
R/W
0
CRCI_EN
Receiver CRC Error Interrupt Enable
0: Disable