Allwinner A20 - Page 653

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 653 / 812
Offset: 0x30
Register Name: IR_RXSTA
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
This bit is cleared by writing a ‘1’.
3
R/W
0
CRC
Receiver CRC Error Flag
0: No CRC failure
1: CRC failure
This bit is cleared by writing a ‘1’.
2
R/W
0
RIS
Receiver Illegal Symbol Flag
0: No illegal symbols in address, control, data or CRC field
1: Illegal symbol in address, control, data or CRC field
This bit is cleared by writing a ‘1’.
1
R/W
0
RPE
Receiver Packet End Flag
0: STO was not detected. In CIR mode, one CIR symbol is
receiving or not detected.
1: STO field or packet abort symbol (7’b0000,000 and
8’b0000,0000 for MIR and FIR) is detected. In CIR mode, one
CIR symbol is received.
This bit is cleared by writing a ‘1’.
0
R/W
0
ROI
Receiver FIFO Overrun
0: Receiver FIFO not overrun
1: Receiver FIFO overrun
This bit is cleared by writing a ‘1’.
6.6.3.14. CIR CONFIGURE REGISTER
Offset: 0x34
Register Name: IR_CIR
Default Value: 0x0000_1828
Bit
Read/Write
Default
Description
31:25
/
/
/
24
R/W
0x0
SCS2
Bit2 of Sample Clock Select for CIR
This bit is defined by SCS bits below.