A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 662 / 812
Register Name: HCCPARAMS
Default Value: Implementation Dependent
IST
Isochronous Scheduling Threshold
This field indicates, relative to the current position of the
executing host controller, where software can reliably update
the isochronous schedule.
When bit[7] is zero, the value of the least significant 3 bits
indicates the number of micro-frames a host controller can
hold a set of isochronous data structures(one or more) before
flushing the state. When bit[7] is a one, then host software
assumes the host controller may cache an isochronous data
structure for an entire frame.
Reserved
These bits are reserved and should be set to zero.
ASPC
Asynchronous Schedule Park Capability
If this bit is set to a one, then the host controller supports the
park feature for high-speed queue heads in the Asynchronous
Schedule. The feature can be disabled or enabled and set to a
specific level by using the Asynchronous Schedule Park Mode
Enable and Asynchronous Schedule Park Mode Count fields
in the USBCMD register.
PFLF
Programmable Frame List Flag
If this bit is set to a zero, then system software must use a
frame list length of 1024 elements with this host controller.The
USBCMD register
Frame List Size field is a read-only register and should be set
to zero.
If set to 1,then system software can specify and use the frame
list in the
USBCMD register Frame List Size field to cofigure the host
controller.
The frame list must always aligned on a 4K page
boundary.This requirement ensures that the frame list is
always physically contiguous.
Reserved
These bits are reserved for future use and should return a
value of zero when read.
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