Allwinner A20 - Page 670

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6.8.5.8. EHCI USB INTERRUPT ENABLE REGISTER
Offset: 0x18
Register Name: USBINTR
Default Value:0x00000000
Bit
Read/Write
Default
Description
31:6
/
0
Reserved
These bits are reserved and should be zero.
5
R/W
0
IAAE
Interrupt on Async Advance Enable
When this bit is 1, and the Interrupt on Async Advance bit in
the USBSTS register is 1, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the Interrupt on Async
Advance bit.
4
R/W
0
HSEE
Host System Error Enable
When this bit is 1, and the Host System Error Status bit in the
USBSTS register is 1, the host controller will issue an interrupt.
The interrupt is acknowledged by software clearing the Host
System Error bit.
3
R/W
0
FLRE
Frame List Rollover Enable
When this bit is 1, and the Frame List Rollover bit in the
USBSTS register is 1, the host controller will issue an interrupt.
The interrupt is acknowledged by software clearing the Frame
List Rollover bit.
2
R/W
0
PCIE
Port Change Interrupt Enable
When this bit is 1, and the Port Chang Detect bit in the
USBSTS register is 1, the host controller will issue an interrupt.
The interrupt is acknowledged by software clearing the Port
Chang Detect bit.
1
R/W
0
EIE
USB Error Interrupt Enable
When this bit is 1, and the USBERRINT bit in the USBSTS
register is 1,the host controller will issue an interrupt at the
next interrupt threshold.
The interrupt is acknowledged by software clearing the
USBERRINT bit.
0
R/W
0
UIE
USB Interrupt Enable
When this bit is 1, and the USBINT bit in the USBSTS register