EasyManua.ls Logo

Allwinner A20 - Page 676

Allwinner A20
812 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 676 / 812
Offset: 0x54
Register Name: PORTSC
Default Value: 0x00002000(w/PPC set to
one);0x00003000(w/PPC set to a zero)
Bit
Read/Write
Default
Description
0x
Disable
10
Enable
11
Suspend
When in suspend state, downstream propagation of data is
blocked on this port, except for port reset. The blocking occurs
at the end of the current transaction, if a transaction was in
progress when this bit was written to 1. In the suspend state,
the port is sensitive to resume detection. Not that the bit status
does not change until the port is suspend and that there may
be a delay in suspending a port if there is a transaction
currently in progress on the USB.
A write of zero to this bit is ignored by the host controller. The
host controller will unconditionally set this bit to a zero when:
1) Software sets the Force Port Resume bit to a zero(from a
one).
2) Software sets the Port Reset bit to a one(from a zero).
If host software sets this bit to a one when the port is not
enabled(i.e. Port enabled bit is a zero), the results are
undefined.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
6
R/W
0
FPR
Force Port Resume
1 = Resume detected/driven on port. 0 = No resume (K-state)
detected/ driven on port. Default value = 0.
This functionality defined for manipulating this bit depends on
the value of the Suspend bit. For example, if the port is not
suspend and software transitions this bit to a one, then the
effects on the bus are undefined.
Software sets this bit to a 1 drive resume signaling. The Host
Controller sets this bit to a 1 if a J-to-K transition is detected
while the port is in the Suspend state. When this bit transitions
to a one because a J-to-K transition is detected, the Port
Change Detect bit in the USBSTS register is also set to a one.
If software sets this bit to a one, the host controller must not
set the Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume
sequence follows the defined sequence documented in the
USB Specification Revision 2.0. The resume signaling
(Full-speed ‘K’) is driven on the port as long as this remains a

Table of Contents