PR
Port Reset
1=Port is in Reset. 0=Port is not in Reset. Default value = 0.
When software writes a one to this bit (from a zero), the bus
reset sequence as defined in the USB Specification Revision
2.0 is started. Software writes a zero to this bit to terminate the
bus reset sequence. Software must keep this bit at a one long
enough to ensure the reset sequence, as specified in the USB
Specification Revision 2.0, completes. Notes: when software
writes this bit to a one , it must also write a zero to the Port
Enable bit.
Note that when software writes a zero to this bit there may be
a delay before the bit status changes to a zero. The bit status
will not read as a zero until after the reset has completed. If the
port is in high-speed mode after reset is complete, the host
controller will automatically enable this port (e.g. set the Port
Enable bit to a one). A host controller must terminate the reset
and stabilize the state of the port within 2 milliseconds of
software transitioning this bit from a one to a zero. For
example: if the port detects that the attached device is
high-speed during reset, then the host controller must have the
port in the enabled state with 2ms of software writing this bit to
a zero.
The HC Halted bit in the USBSTS register should be a zero
before software attempts to use this bit. The host controller
may hold Port Reset asserted to a one when the HC Halted bit
is a one.
This field is zero if Port Power is zero.
To Next Page
Loading...