Allwinner A20 - Page 680

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6.8.7.2. HCCONTROL REGISTER
Offset: 0x404
Register Name: HcRevision
Default Value:0x0
Bit
Read/Write
Default
Description
HCD
HC
31:11
Reserved
10
R/W
R
0x0
RemoteWakeupEnable
This bit is used by HCD to enable or disable the remote wakeup
feature upon the detection of upstream resume signaling. When
this bit is set and the ResumeDetected bit in HcInterruptStatus is
set, a remote wakeup is signaled to the host system. Setting this bit
has no impact on the generation of hardware interrupt.
9
R/W
R/W
0x0
RemoteWakeupConnected
This bit indicates whether HC supports remote wakeup signaling. If
remote wakeup is supported and used by the system, it is the
responsibility of system firmware to set this bit during POST. HC
clear the bit upon a hardware reset but does not alter it upon a
software reset. Remote wakeup signaling of the host system is
host-bus-specific and is not described in this specification.
8
R/W
R
0x0
InterruptRouting
This bit determines the routing of interrupts generated by events
registered in HcInterruptStatus. If clear, all interrupt are routed to
the normal host bus interrupt mechanism. If set interrupts are
routed to the System Management Interrupt. HCD clears this bit
upon a hardware reset, but it does not alter this bit upon a software
reset. HCD uses this bit as a tag to indicate the ownership of HC.
7:6
R/W
R/W
0x0
HostControllerFunctionalState for USB
00
b
USBReset
01
b
USBResume
10
b
USBOperational
11
b
USBSuspend
A transition to USBOperational from another state causes SOF
generation to begin 1 ms later. HCD may determine whether HC
has begun sending SOFs by reading the StartoFrame field of
HcInterruptStatus.
This field may be changed by HC only when in the USBSUSPEND
state. HC may move from the USBSUSPEND state to the
USBRESUME state after detecting the resume signaling from a
downstream port.
HC enters USBSUSPEND after a software reset, whereas it enters
USBRESET after a hardware reset. The latter also resets the Root
Hub and asserts subsequent reset signaling to downstream ports.
BulkListEnable
This bit is set to enable the processing of the Bulk list in the next
Frame. If cleared by HCD, processing of the Bulk list does not
occur after the next SOF. HC checks this bit whenever it
determines to process the list. When disabled, HCD may modify
the list. If HcBulkCurrentED is pointing to an ED to be removed,