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5
R/W
R
0x0
HCD must advance the pointer by updating HcBulkCurrentED
before re-enabling processing of the list.
4
R/W
R
0x0
ControlListEnable
This bit is set to enable the processing of the Control list in the next
Frame. If cleared by HCD, processing of the Control list does not
occur after the next SOF. HC must check this bit whenever it
determines to process the list. When disabled, HCD may modify
the list. If HcControlCurrentED is pointing to an ED to be removed,
HCD must advance the pointer by updating HcControlCurrentED
before re-enabling processing of the list.
3
R/W
R
0x0
IsochronousEnable
This bit is used by HCD to enable/disable processing of
isochronous EDs. While processing the periodic list in a Frame, HC
checks the status of this bit when it finds an Isochronous ED (F=1).
If set (enabled), HC continues processing the EDs. If cleared
(disabled), HC halts processing of the periodic list (which now
contains only isochronous EDs) and begins processing the
Bulk/Control lists.
Setting this bit is guaranteed to take effect in the next Frame (not
the current Frame).
2
R/W
R
0x0
PeriodicListEnable
This bit is set to enable the processing of periodic list in the next
Frame. If cleared by HCD, processing of the periodic list does not
occur after the next SOF. HC must check this bit before it starts
processing the list.
1:0
R/W
R
0x0
ControlBulkServiceRatio
This specifies the service ratio between Control and Bulk EDs.
Before processing any of the nonperiodic lists, HC must compare
the ratio specified with its internal count on how many nonempty
Control EDs have been processed, in determining whether to
continue serving another Control ED or switching to Bulk EDs. The
internal count will be retained when crossing the frame boundary.
In case of reset, HCD is responsible for restoring this value.
CBSR
No. of Control EDs Over Bulk EDs Served
0
1:1
1
2:1
2
3:1
3
4:1
The default value is 0x0.
6.8.7.3. HCCOMMANDSTATUS REGISTER
Offset: 0x408
Register Name: HcCommandStatus
Default Value:0x0
Bit
Read/Write
Default
Description
HCD
HC
31:18
Reserved
SchedulingOverrunCount
These bits are incremented on each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. This will be
incremented when a scheduling overrun is detected even if