Allwinner A20 - Page 69

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 69 / 812
01: PLL2(4X)
10: PLL2(2X)
11: PLL2(1X)
15:0
/
/
/.
1.5.4.36. AC97 CLOCK(DEFAULT: 0X00030000)
Offset: 0xBC
Register Name: AC97_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON
30:18
/
/
/
17:16
R/W
0x3
CLK_SRC_SEL.
00: PLL2 (8x)
01: PLL2(4X)
10: PLL2(2X)
11: PLL2(1X)
15:0
/
/
/.
1.5.4.37. KEYPAD CLOCK(DEFAULT: 0X0000001F)
Offset: 0xC4
Register Name: KEYPAD_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 100MHz)
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
0: OSC24M