Allwinner A20 - Page 702

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 702 / 812
Offset: 0x00
Register Name: DA_CTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
Globe Enable
A disable on this bit overrides any other block or channel
enables.
0: Disable
1: Enable
6.9.5.2. DIGITAL AUDIO FORMAT REGISTER 0
Offset: 0x04
Register Name: DA_FAT0
Default Value: 0x0000_000C
Bit
Read/Write
Default
Description
31:8
/
/
/
7
R/W
0
LRCP
Left/ Right Clock Parity
0: Normal
1: Inverted
In DSP/ PCM mode
0: MSB is available on 2nd BCLK rising edge after LRC rising
edge
1: MSB is available on 1st BCLK rising edge after LRC rising
edge
6
R/W
0
BCP
BCLK Parity
0: Normal
1: Inverted
5:4
R/W
0
SR
Sample Resolution
00: 16-bit
01: 20-bit
10: 24-bit
11: Reserved
3:2
R/W
0x3
WSS
Word Select Size