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Allwinner A20 - Page 704

Allwinner A20
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A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 704 / 812
Offset: 0x08
Register Name: DA_FAT1
Default Value: 0x0000_4020
Bit
Read/Write
Default
Description
MSB / LSB First Select
0: MSB First
1: LSB First
8
R/W
0
SEXT
Sign Extend (only for 16 bits slot)
0: Zeros or audio gain padding at LSB position
1: Sign extension at MSB position
When writing the bit is 0, the unused bits are audio gain for
13-bit linear sample and zeros padding for 8-bit companding
sample.
When writing the bit is 1, the unused bits are both sign
extension.
7:6
R/W
0
SI
Slot Index
00: the 1st slot
01: the 2nd slot
10: the 3rd slot
11: the 4th slot
5
R/W
1
SW
Slot Width
0: 8 clocks width
1: 16 clocks width
Note: For A-law or u-law PCM sample, if this bit is set to 1,
eight zero bits are following with PCM sample.
4
R/W
0
SSYNC
Short Sync Select
0: Long Frame Sync
1: Short Frame Sync
It should be set ‘1’ for 8 clocks width slot.
3:2
R/W
0
RX_PDM
PCM Data Mode
00: 16-bits Linear PCM
01: 8-bits Linear PCM
10: 8-bits u-law
11: 8-bits A-law

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