Allwinner A20 - Page 708

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 708 / 812
Offset: 0x18
Register Name: DA_FSTA
Default Value: 0x1080_0000
Bit
Read/Write
Default
Description
6:0
R
0
RXA_CNT
RX FIFO Available Sample Word Counter
6.9.5.8. DIGITAL AUDIO DMA & INTERRUPT CONTROL REGISTER
Offset: 0x1C
Register Name: DA_INT
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
7
R/W
0
TX_DRQ
TX FIFO Empty DRQ Enable
0: Disable
1: Enable
6
R/W
0
TXUI_EN
TX FIFO Under run Interrupt Enable
0: Disable
1: Enable
5
R/W
0
TXOI_EN
TX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, an interrupt happens when writing new audio
data if TX FIFO is full.
4
R/W
0
TXEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable
3
R/W
0
RX_DRQ
RX FIFO Data Available DRQ Enable
0: Disable
1: Enable
When set to ‘1’, RXFIFO DMA Request line is asserted if Data
is available in RX FIFO.