Allwinner A20 - Page 71

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 71 / 812
Bit
Read/
Write
Default/Hex
Description
31:9
/
/
/
8
R/W
0x0
SCLK_GATING_USBPHY.
Gating Special Clock for USB PHY0/1/2
0: Clock is OFF
1: Clock is ON
7
R/W
0x0
SCLK_GATING_OHCI1.
Gating Special Clock for OHCI1
0: Clock is OFF
1: Clock is ON
6
R/W
0x0
SCLK_GATING_OHCI0.
Gating Special Clock for OHCI0
0: Clock is OFF
1: Clock is ON
5:3
/
/
/.
2
R/W
0x0
USBPHY2_RST.
USB PHY2 Reset Control
0: Reset valid
1: Reset invalid
1
R/W
0x0
USBPHY1_RST.
USB PHY1 Reset Control
0: Reset valid
1: Reset invalid
0
R/W
0x0
USBPHY0_RST.
USB PHY0 Reset Control
0: Reset valid
1: Reset invalid
1.5.4.40. SPI3 CLOCK(DEFAULT: 0X00000000)
Offset: 0xD4
Register Name: SPI3_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)