Allwinner A20 - Page 711

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 711 / 812
Offset: 0x24
Register Name: DA_CLKD
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
000: Divide by 2 (BCLK = MCLK/2)
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 12
101: Divide by 16
110: Divide by 32
111: Divide by 64
3:0
R/W
0
MCLKDIV
MCLK Divide Ratio from Audio PLL Output
0000: Divide by 1
0001: Divide by 2
0010: Divide by 4
0011: Divide by 6
0100: Divide by 8
0101: Divide by 12
0110: Divide by 16
0111: Divide by 24
1000: Divide by 32
1001: Divide by 48
1010: Divide by 64
Others : Reserved
6.9.5.11. DIGITAL AUDIO TX COUNTER REGISTER
Offset: 0x28
Register Name: DA_TXCNT
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R/W
0
TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO. When one
sample is put into TXFIFO by DMA or by host IO, the TX
sample counter register increases by one. The TX sample
counter register can be set to any initial valve at any time. After