Allwinner A20 - Page 73

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 73 / 812
Offset: 0xD8
Register Name: IIS1_CLK_REG
Bit
Read/
Write
Default/Hex
Description
10: PLL2(2X)
11: PLL2(1X)
15:0
/
/
/.
1.5.4.42. IIS2 CLOCK(DEFAULT: 0X00000000)
Offset: 0xDC
Register Name: IIS2_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON
30:18
/
/
/
17:16
R/W
0x0
CLK_SRC_SEL.
00: PLL2 (8x)
01: PLL2(4X)
10: PLL2(2X)
11: PLL2(1X)
15:0
/
/
/.
1.5.4.43. DRAM CLK(DEFAULT: 0X00000000)
Offset: 0x100
Register Name: DRAM_CLK_REG
Bit
Read/
Write
Default/Hex
Description
31:30
/
/
/
29
R/W
0x0
ACE_DCLK_GATING.
Gating DRAM Clock for ACE(0: mask, 1: pass).
28
R/W
0x0
DE_MP_DCLK_GATING.
Gating DRAM Clock for DE_MP(0: mask, 1: pass).
27
R/W
0x0
BE1_DCLK_GATING.
Gating DRAM Clock for DE_BE1(0: mask, 1: pass).