Allwinner A20 - Page 74

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 74 / 812
Offset: 0x100
Register Name: DRAM_CLK_REG
Bit
Read/
Write
Default/Hex
Description
26
R/W
0x0
BE0_DCLK_GATING.
Gating DRAM Clock for DE_BE0(0: mask, 1: pass).
25
R/W
0x0
FE0_DCLK_GATING.
Gating DRAM Clock for DE_FE1(0: mask, 1: pass).
24
R/W
0x0
FE1_DCLK_GATING.
Gating DRAM Clock for DE_FE0(0: mask, 1: pass).
23:16
/
/
/
15
R/W
0x0
DCLK_OUT_EN.
DRAM Clock Output Enable(0: disable, 1: enable)
14:7
/
/
/
6
R/W
0x0
TVE1_DCLK_GATING.
Gating DRAM Clock for TVE 1(0: mask, 1: pass).
5
R/W
0x0
TVE0_DCLK_GATING.
Gating DRAM Clock for TVE 0(0: mask, 1: pass).
4
R/W
0x0
TVD_DCLK_GATING.
Gating DRAM Clock for TVD(0: mask, 1: pass).
3
R/W
0x0
TS_DCLK_GATING.
Gating DRAM Clock for TS(0: mask, 1: pass).
2
R/W
0x0
CSI1_DCLK_GATING.
Gating DRAM Clock for CSI1(0: mask, 1: pass).
1
R/W
0x0
CSI0_DCLK_GATING.
Gating DRAM Clock for CSI0(0: mask, 1: pass).
0
R/W
0x0
VE_DCLK_GATING.
Gating DRAM Clock for VE(0: mask, 1: pass).
1.5.4.44. DE-BE 0 CLOCK(DEFAULT: 0X00000000)
Offset: 0x104
Register Name: BE0_SCLK_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock