Allwinner A20 - Page 733

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 733 / 812
Offset: 0x18
Register Name: AC_FCTL
Default Value: 0x0000_3078
Bit
Read/Write
Default
Description
Write “1” to flush TX FIFO, self clear to “0”
16
R/W
0
FRX
Write “1” to flush RX FIFO, self clear to “0”
15:8
R/W
0x30
TXTL
TX FIFO empty Trigger Level
Interrupt and DMA request trigger level for TX FIFO
normal condition
Trigger Level = TXTL
7:3
R/W
0x0F
RXTL
RX FIFO Trigger Level
Interrupt and DMA request trigger level for RX FIFO
normal condition
Trigger Level =RXTL + 1
2
R/W
0
TXIM
TX FIFO Input Mode(Mode0, 1)
0: Valid data at the MSB of AC_TXFIFO register
1: Valid data at the LSB of AC_TXFIFO register
Example for 18-bits transmitted audio sample:
Mode 0: FIFO_I[19:0] = {TXFIFO[31:14], 2’h0}
Mode 1: FIFO_I[19:0] = {TXFIFO[17:0], 2’h0}
1:0
R/W
0
RXOM
RX FIFO Output Mode(Mode 0,1,2,3)
00: Expanding “0” at LSB of AC_RXFIFO register
01: Expanding received sample sign bit at MSB of
AC_RXFIFO register
10: Truncating received samples at high half-word of
AC_RXFIFO register and low half-word of AC_FIFO
register is filled by “0”
11: Truncating received samples at low half-word of
AC_RXFIFO register and high half-word of AC_FIFO
register is expanded by its sigh bit
Example for 18-bits received audio sample:
Mode0: RXFIFO[31:0] = {FIFO_O[19:2], 14’h0}
Mode 1: RXFIFO[31:0] = {14’FIFO_O[19], FIFO_O[19:2]}
Mode 2: RXFIFO[31:0] = {FIFO_O[19:4], 16’h0}
Mode 3: RXFIFO[31:0] = {16’FIFO_O[19], FIFO_O[19:4]}