Allwinner A20 - Page 750

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 750 / 812
Offset: 0x10
Register Name: TSC_PCTLR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
0 – SPI
1 – SSI
6.13.4.4. TSC PORT PARAMETER REGISTER
Offset: 0x14
Register Name: TSC_PPARR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:24
R/W
0x00
TSOutPort0Par
TS Output Port0 Parameters
Bit
Definition
7:5
/
4
SSI data order
0: MSB first for one byte data
1: LSB first for one byte data
3
CLOCK signal polarity
0 : Rise edge capturing
1: Fall edge capturing
2
ERROR signal polarity
0: High level active
1: Low level active
1
DVALID signal polarity
0: High level active
1: Low level active
0
PSYNC signal polarity
0: High level active
1: Low level active
23:16
/
/
/
15:8
R/W
0x00
TSInPort1Par
TS Input Port1 Parameters
Bit
Definition
7:5
Reserved
4
SSI data order
0: MSB first for one byte data
1: LSB first for one byte data
3
CLOCK signal polarity
0 : Rise edge capturing
1: Fall edge capturing
2
ERROR signal polarity
0: High level active
1: Low level active